Based on your technology process, be it single or multi-wafer, and further taking into account the intent or design objective of your testchip – including use cases and overall bench evaluation needs, we draw up a concept. The span of this phase usually ranges from days and up to a few weeks, depending on the complexity and size of your testchip. The concept includes a bill of materials (BOM) – e.g. for VIP required, all the interfaces, analog modelling strategy, functional verification strategy, global architecture of the verification and validation, and ballpark effort estimations with high level planning.
VERIFICATION SERVICES
CHIPAHEAD’s founders developed their verification expertise on aspect-oriented e-language and the eRM methodology. Our engineers’ experience grew through a vast array of complex projects, in major verification methodologies, such eRM, OVM, VMM and UVM. All our engineers have conducted verification with SystemVerilog and the UVM methodology.
In recent years, the increased adoption of advanced verification methodologies in complex analog-mixed-signal (AMS) SoCs has unveiled new opportunities to reuse proven techniques employed in large digital SoC verification. Bringing the analog and digital disciplines together in order to deliver verification and efficient validation requires substantial seniority and experience, with multiple flows – such as digital on top, analog on top, or integration with specific EDA like Cadence’s Virtuoso, to list only a few.
Our engineering have conducted verification for AMS SoCs with large digital content (multiple MCUs and DSPs), gaining experience in analog modelling techniques, such as RNM with Verilog-AMS, and all the development steps, from model planning (accuracy, precision, speed), to model development and calibration.
CHIPAHEAD’s verification engineering experience is the ideal partner for startups developing new products. We look at individual Customer business cases, product features and associated use cases, requirements and constraints, flows and other technological needs. We are then able to quote a complete verification package taking into account major milestones ranging from planning and up to sign-off, with a mutually beneficial business model that can include shared risks.
IP Verification
IP functional verification addresses both newly designed IP and existing IP that requires adaptation - e.g. an IP with a proprietary bus that needs to be AXI ready. The goal is to deliver fully documented verification infrastructure for the IP including out-of-the-box (OOB) testbench, enabling fast reuse - e.g. at SoC level. Hence, apart from guaranteeing the IP functionality, a great amount of attention is paid in the definition of use cases that constitute the OOB testbench.
Subsystem Verification
The combined complexity of multiple IP at the sub-system level can be huge and, already at this stage, there are many seemingly independent activities that need to be closely correlated. Sub-system IP verification requires the definition of complicated test scenarios, as well as measuring how well we trigger such scenarios and corner cases. Sub-system IP will typically be delivered into SoC. Finally, controlling SoC verification effort, in order to meet tight market windows, requires pre-verified IP with sub-system IP. That can be an opportunity if previously verified or a challenge that will otherwise need addressing.
SoC Verification
SoC’s may take many shapes, depending on markets or choice of architecture, to name a few of the variables. A typical SOC may contain processors or even processor sub-system, processor and peripheral buses, bridges between buses, and, in many cases, complex interconnects, coherent or not, which on their own have the complexity of a sub-system IP. Large SoCs have one or multiple instantiations of hundreds of IP. SoC verification builds typically from the assumption of existing pre-verified IP and sub-system IP, even in the common case where IP is being verified in parallel with the SoC verification. The primary focus when conducting SoC verification is on validating the integration between the various IP by exercising use cases at the SoC level.
Planning
Detailed Planning
Implementation
Verification
Sign-Off
Planning
Detailed Planning
We conduct a detailed investigation, based on an original concept, which will deliver, among others: verification and test case planning (V&TP) for IP and/or Subsystem IP and V&TP for SoC level, including functional use cases, design for debug and/or characterization (typically through analog muxes) and required tests to demonstrate DFT (e.g. scan) before TO. Black-box specifications of analog models are produced as well, based on specific requirements (accuracy, precision, speed). Also delivered at this stage is a detailed project plan, along with a risk list.
Implementation
The implementation phase brings up to three parallel developments: analog modelling, testbench creation with instantiation of DUT and required VIPs, and testcase coding. When the testchip includes a MCU, a fourth parallel development entails setting-up the tool chain and writing simple firmware routines, in order to ensure high controllability and observability of internal interconnection within the testchip. Our progress is now tracked by the maturity of the design provided by your design team, our analog modelling (planned, coded, calibrated), along with testcase status (planned, coded, passing). Further on, it is reported based on verification metrics, such as functional coverage and indicators like cumulative bug curves. Independently of the engagement model agreed upon at the start, we ensure that changes, e.g. specification changes, are accurately tracked throughout the project and reviewed in order to manage effort and lead time.
Verification
A large amount of the development cycle is typically spent on verification. It is also during this phase that uncertainty requires strict management. Our experience contributes to decreasing debug times and hence de-risk uncertainty. This phase tends to overlap with the implementation phase. We usually start verification as early as a register bank for the chip is in place, along with at least one interface, allowing us to start exercising the SoC. At the start of the verification phase, we aim to assemble regressions for different use cases, as well as a sanity regression. Our objective is to enable quick changes in the design (digital and analog models), based on last minute changes required by your end Customer or on evolving target market needs. At RTL freeze milestone we will continue to push on verification while your Team focuses on top-level verification and chip finishing. Concise tracking of verification progress and closure driven by metrics and shared via dashboard will guide the project to its conclusion.
Sign-Off
Through peer reviews of plans versus implementation, simulation results and metric status, testcase status, design requirement versus testbench implementation checks, we jointly assess the maturity and likelihood of delivering a successful TO.
Processes
Main processes in place include:
- Verification development process for IP (VDPIP)
- Verification development process for Subsystem IP (VDPSSIP)
- Verification development process for SoC (VDPSOC)
- Analog modelling: planning, development and calibration
- Verification closure: metrics and criteria user guide
- Project management guidelines
- Effort estimation, planning and reporting guidelines
- Risk and uncertainty management in verification
- Verification planning for ISO26262
EDA
Experienced with major EDA and tools such as:
- Synopsys: VCS, Formality
- Mentor: Questa, Modelsim, VRM
- Cadence: Incisive, Xcelium, Specman, vManager, vPlanner, JasperGold
- Simulink (MathWorks)
- GCC
- Jira, Bugzilla
- SVN, Clearcase, Git, Perforce
- Jama, ReqTracer
- Jenkins
Experience
CHIPAHEAD’s engineering has completed verification of designs with:
- Memory PHY & Controller IPs based on Jedec standards such as GDDR6, [LP]DDR4/5
- MCUs such as ARM’s M0 and M4
- Interface IP such as Gigabit
- Ethernet and PCIe Interconnect IP based on AXI and AHB
- MIPI IPs such as CSI2 & DSI
- Ultrasound Imaging System
- Audio ANC processing
- Time Of Flight (ToF) sensors
- DSP & NPU for AI/ML
- ISO26262 Automotive sensors
- Video & Graphics Processor